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Alimoradi, Adel, Rostami, Pourya, Karami, Manoocheher (2018) Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits. International Journal of Computer Applications, 179. 39-43 doi:10.5120/ijca2018916476

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Reference TypeJournal (article/letter/editorial)
TitleNovel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits
JournalInternational Journal of Computer Applications
AuthorsAlimoradi, AdelAuthor
Rostami, PouryaAuthor
Karami, ManoocheherAuthor
Year2018 (February 15)Volume179
PublisherFoundation of Computer Science
DOIdoi:10.5120/ijca2018916476Search in ResearchGate
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Mindat Ref. ID6533656Long-form Identifiermindat:1:5:6533656:4
GUID0
Full ReferenceAlimoradi, Adel, Rostami, Pourya, Karami, Manoocheher (2018) Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits. International Journal of Computer Applications, 179. 39-43 doi:10.5120/ijca2018916476
Plain TextAlimoradi, Adel, Rostami, Pourya, Karami, Manoocheher (2018) Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits. International Journal of Computer Applications, 179. 39-43 doi:10.5120/ijca2018916476
In(2017) International Journal of Computer Applications Vol. 179. Foundation of Computer Science

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Tauseef, Md., Sharma, Sudeep, Jain, Rita (2016) A Novel Leakage Reduction Technique for Ultra-low Power in VLSI Circuit. International Journal of Computer Applications, 148. 29-34 doi:10.5120/ijca2016911090
Saini, Pushpa, Mehra, Rajesh (2012) Leakage Power Reduction in CMOS VLSI Circuits. International Journal of Computer Applications, 55. 42-48 doi:10.5120/8778-2721
LeelaRani, V., Madhavi Latha, M., Sai Ramesh, A. (2012) Galeorstack- A Novel Leakage Reduction Technique for Low Power VLSI Design. International Journal of Computer Applications, 48. 29-38 doi:10.5120/7370-0146
S.Aswale, P., S. Chopade, S. (2013) Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits. International Journal of Computer Applications, 70. 16-24 doi:10.5120/12005-6866
Saini, Pushpa, Mehra, Rajesh (2012) A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits. International Journal of Advanced Computer Science and Applications, 3. doi:10.14569/ijacsa.2012.031026
VaraPrasadDone, Manikya, Panwar, Uday, Khare, Kavita (2014) An Algorithm for Leakage Power Reduction through IVC in CMOS VLSI Digital Circuits. International Journal of Computer Applications, 94. 24-28 doi:10.5120/16356-5740
H.P., Rajani, Y. Kulkarni, S. (2012) LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design. International Journal of Computer Applications, 51. 42-49 doi:10.5120/8145-1931
Sailaja, K., Leela Rani, V., Mahammad Akram, Sk. (2013) Analysis of Leakage Power Reduction Techniques for Low Power VLSI Design. International Journal of Computer Applications, 82. 20-23 doi:10.5120/14264-2408
Upasani, Dhananjay E., Shrote, Sandip B., Deshpande, Pallavi S. (2010) Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits. International Journal of Computer Applications, 7. 1-4 doi:10.5120/1162-1467
Karpagam, G., E.Konguvel, E.Konguvel, M.Thangamani, M.Thangamani (2015) A Low Power VLSI Implementation of STTRAM based TCAM for High Speed Switching Circuits. International Journal of Computer Applications, 115. 38-42 doi:10.5120/20167-2299
Panwar, Uday, Vishnoi, Himanshu (2017) Diode Switch: A Novel Technique for Mitigation of Leakage Power in DSM Technologies. International Journal of Computer Applications, 167. 13-19 doi:10.5120/ijca2017914209
 
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